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Introduction to Altera FPGAs

Let's talk about Altera and their FPGA and tooling offerings.

Hardware​

The FPGA offerings of Altera are divided into the following groups / product lines:

  • Agilex / Stratix: The high performance FPGAs for networking and high performance computing
  • Arria: The middle ground between price and performance
  • Cyclone: The low-end for power and price sensitive applications

This series is mainly focussed around the Cyclone series of FPGAs due to the fact that I have access to them.

Software​

Unfortunately, FPGAs can't do much of anything without a way of programming them. This is where the tooling comes in and where it gets exciting from a software standpoint.

Quartus​

Let's talk about the star of the show: The Quartus Prime design software. It is the heart of the hardware and software development flow for Altera FPGAs.

Quartus houses all other tools that are needed to develop and debug FPGA designs. It contains synthesis tools, optimizers, assemblers, timing analyzers and tons of tools to view the results of your design and what the compiler thinks of it. To say that this piece of software is a behemoth is a bold understatement. It comes with tons of analysis tools such as:

  • TimeQuest: The timing analyzer to see how long signals take from A to B, etc
  • SignalTap: An in-chip logic analyzer that can be introduced into the design to perform on-chip debugging
  • RTL Logic viewers: View the logic that is being generated down to the individual logic gates
  • State Machine Viewers: Quartus can detect state machines in your design and show the states and all transitions
  • Memory Content Analysis: Analyze the memory contents and allocation for your design
  • Statistics: Provide statistics about your design, such as logic and memory usage, etc

This is only scratching the surface. There is literally tons of sub-tools and endless menus that almost scream for experimentation.

All of this comes at a cost, however: complexity. Getting the hang of this piece of software is not easy and requires quite some learning and getting used-to, but once you understand how to work with it, it becomes even more powerful.

Platform Designer​

Platform Designer is a piece of software that is integrated into Quartus but is in itself a stand-alone system.

It provides functionality to create complete systems that consist of different IP blocks. This is what we will use for creating our soft-core and its peripherals.

It essentially takes the burden of the FPGA engineer to manually connect thousands of pins and signals between IP core blocks. Additionally, it provides a nice interface for instantiating the NIOS family of soft-cores. You can route memory buses around, set base addresses and create connections that exit from the system and go to other parts of your design.

Additionally, this piece of software can generate system information that can later be used to automatically generate drivers and base address definitions for the software that is to run on the generated CPUs. This is actually quite useful and we will take advantage of this mechanism when we create our system later in this series.

NIOS Tools​

As already said, the NIOS is the soft-core provided by Altera. Quartus contains tooling for creating and compiling projects for these soft-cores. Some tools create bridges between the FPGA logic and the software that runs on it, such as:

  • Creating base address information files in the form of C headers
  • Instantiating and configuring drivers for the IP cores, if desired
  • Providing linking information in the form of a linker script
  • Providing startup code for the processor core

And much more, such as ways for interfacing with the soft-core via JTAG, logging, etc.

The NIOS​

Let's talk about what you are probably here for: The NIOS processor.

Altera has 3 generations of soft-cores available:

  • The deprecated NIOS
  • The newer NIOS-II
  • The latest (and the one we want) NIOS-V

The NIOS-V​

In 2023 Altera (then Intel) announced a new soft-core for their FPGAs that is based on the RISC-V architecture. This has since been realized in the form of the NIOS-V soft-core.

The NIOS-V comes in 3 flavors:

  • NIOS-V/c: Compact implementation for minimal footprint
  • NIOS-V/m: Micro controller variant that has some more power, but balances its footprint
  • NIOS-V/g: General-purpose CPU capable of running Linux, maximum speed for more area

These CPU implement two different RISC-V variants:

  • NIOS-V/c and NIOS-V/m: RISCV-I
  • NIOS-V/g: RISCV-IM